The present invention relates to multi-core system-on-a-chip integrated circuits, and more particularly to integrated circuits having a digital signal processor subsystem and multiple cores sharing direct access to the same memory.
Wireless, imaging and broadband communications processing systems commonly use both signal and logical processing operations. Architectures suited to one type of processing are typically not suited or appropriate for the other. General-purpose architectures are limited both in flexibility and efficiency for digital signal processor, DSP, operations. DSP architectures, developed for arithmetic operations, are not optimal in functions with extensive bit level manipulations. Heterogeneous architectures, that is integrated circuits having both types of cores, provide one solution to this tradeoff.
For example, in a wireless communications system, the transmitted signals are normally encoded with error protection codes. When such signals are received, they must first be decoded to recover the transmitted information. Decoding is a bit level process. The decoded or recovered signal is processed by various arithmetic algorithms, e.g. for echo cancellation. Such arithmetic operations are best performed in DSPs.
The tradeoffs are further complicated by the fact that algorithms and standards in many emerging areas of signal processing, especially communications, are evolving. That is, new algorithms are being developed to meet new standards and it is desirable to update systems as soon as possible. In addition, it is desirable that both bit level and DSP processing operations be flexible so that different algorithms may be used for different signal streams which pass through the same system or for the same signal streams at different times. This diversity of processing and need for flexibility and reconfigurability of operation make fully programmable systems attractive to system designers.
In heterogeneous systems, the various cores usually do not all operate at the same clock frequency. DSPs usually operate at the highest clock speed, while bit level logic cores operate at a lower frequency. Cores exchanging data with a DSP through a general-purpose bus must operate at clock speeds limited by the bus. It would be desirable to optimize the data exchanges between a DSP core and other devices to make most efficient use of available bandwidth.